stm32f1xx_ll_bus.h 45 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031
  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_ll_bus.h
  4. * @author MCD Application Team
  5. * @brief Header file of BUS LL module.
  6. @verbatim
  7. ##### RCC Limitations #####
  8. ==============================================================================
  9. [..]
  10. A delay between an RCC peripheral clock enable and the effective peripheral
  11. enabling should be taken into account in order to manage the peripheral read/write
  12. from/to registers.
  13. (+) This delay depends on the peripheral mapping.
  14. (++) AHB & APB peripherals, 1 dummy read is necessary
  15. [..]
  16. Workarounds:
  17. (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
  18. inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
  19. @endverbatim
  20. ******************************************************************************
  21. * @attention
  22. *
  23. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  24. *
  25. * Redistribution and use in source and binary forms, with or without modification,
  26. * are permitted provided that the following conditions are met:
  27. * 1. Redistributions of source code must retain the above copyright notice,
  28. * this list of conditions and the following disclaimer.
  29. * 2. Redistributions in binary form must reproduce the above copyright notice,
  30. * this list of conditions and the following disclaimer in the documentation
  31. * and/or other materials provided with the distribution.
  32. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  33. * may be used to endorse or promote products derived from this software
  34. * without specific prior written permission.
  35. *
  36. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  37. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  38. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  39. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  40. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  41. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  42. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  43. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  44. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  45. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46. *
  47. ******************************************************************************
  48. */
  49. /* Define to prevent recursive inclusion -------------------------------------*/
  50. #ifndef __STM32F1xx_LL_BUS_H
  51. #define __STM32F1xx_LL_BUS_H
  52. #ifdef __cplusplus
  53. extern "C" {
  54. #endif
  55. /* Includes ------------------------------------------------------------------*/
  56. #include "stm32f1xx.h"
  57. /** @addtogroup STM32F1xx_LL_Driver
  58. * @{
  59. */
  60. #if defined(RCC)
  61. /** @defgroup BUS_LL BUS
  62. * @{
  63. */
  64. /* Private types -------------------------------------------------------------*/
  65. /* Private variables ---------------------------------------------------------*/
  66. /* Private constants ---------------------------------------------------------*/
  67. #if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
  68. #define RCC_AHBRSTR_SUPPORT
  69. #endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
  70. /* Private macros ------------------------------------------------------------*/
  71. /* Exported types ------------------------------------------------------------*/
  72. /* Exported constants --------------------------------------------------------*/
  73. /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
  74. * @{
  75. */
  76. /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
  77. * @{
  78. */
  79. #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
  80. #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
  81. #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
  82. #if defined(DMA2)
  83. #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
  84. #endif /*DMA2*/
  85. #if defined(ETH)
  86. #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN
  87. #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN
  88. #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN
  89. #endif /*ETH*/
  90. #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
  91. #if defined(FSMC_Bank1)
  92. #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
  93. #endif /*FSMC_Bank1*/
  94. #if defined(USB_OTG_FS)
  95. #define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN
  96. #endif /*USB_OTG_FS*/
  97. #if defined(SDIO)
  98. #define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
  99. #endif /*SDIO*/
  100. #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
  101. /**
  102. * @}
  103. */
  104. /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
  105. * @{
  106. */
  107. #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
  108. #define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
  109. #if defined(CAN1)
  110. #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
  111. #endif /*CAN1*/
  112. #if defined(CAN2)
  113. #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
  114. #endif /*CAN2*/
  115. #if defined(CEC)
  116. #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
  117. #endif /*CEC*/
  118. #if defined(DAC)
  119. #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
  120. #endif /*DAC*/
  121. #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
  122. #if defined(I2C2)
  123. #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
  124. #endif /*I2C2*/
  125. #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
  126. #if defined(SPI2)
  127. #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
  128. #endif /*SPI2*/
  129. #if defined(SPI3)
  130. #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
  131. #endif /*SPI3*/
  132. #if defined(TIM12)
  133. #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
  134. #endif /*TIM12*/
  135. #if defined(TIM13)
  136. #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
  137. #endif /*TIM13*/
  138. #if defined(TIM14)
  139. #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
  140. #endif /*TIM14*/
  141. #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
  142. #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
  143. #if defined(TIM4)
  144. #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
  145. #endif /*TIM4*/
  146. #if defined(TIM5)
  147. #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
  148. #endif /*TIM5*/
  149. #if defined(TIM6)
  150. #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
  151. #endif /*TIM6*/
  152. #if defined(TIM7)
  153. #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
  154. #endif /*TIM7*/
  155. #if defined(UART4)
  156. #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
  157. #endif /*UART4*/
  158. #if defined(UART5)
  159. #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
  160. #endif /*UART5*/
  161. #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
  162. #if defined(USART3)
  163. #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
  164. #endif /*USART3*/
  165. #if defined(USB)
  166. #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
  167. #endif /*USB*/
  168. #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
  169. /**
  170. * @}
  171. */
  172. /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
  173. * @{
  174. */
  175. #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
  176. #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
  177. #if defined(ADC2)
  178. #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
  179. #endif /*ADC2*/
  180. #if defined(ADC3)
  181. #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
  182. #endif /*ADC3*/
  183. #define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
  184. #define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
  185. #define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
  186. #define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
  187. #define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
  188. #if defined(GPIOE)
  189. #define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
  190. #endif /*GPIOE*/
  191. #if defined(GPIOF)
  192. #define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN
  193. #endif /*GPIOF*/
  194. #if defined(GPIOG)
  195. #define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN
  196. #endif /*GPIOG*/
  197. #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
  198. #if defined(TIM10)
  199. #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
  200. #endif /*TIM10*/
  201. #if defined(TIM11)
  202. #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
  203. #endif /*TIM11*/
  204. #if defined(TIM15)
  205. #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
  206. #endif /*TIM15*/
  207. #if defined(TIM16)
  208. #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
  209. #endif /*TIM16*/
  210. #if defined(TIM17)
  211. #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
  212. #endif /*TIM17*/
  213. #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
  214. #if defined(TIM8)
  215. #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
  216. #endif /*TIM8*/
  217. #if defined(TIM9)
  218. #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
  219. #endif /*TIM9*/
  220. #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
  221. /**
  222. * @}
  223. */
  224. /**
  225. * @}
  226. */
  227. /* Exported macro ------------------------------------------------------------*/
  228. /* Exported functions --------------------------------------------------------*/
  229. /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
  230. * @{
  231. */
  232. /** @defgroup BUS_LL_EF_AHB1 AHB1
  233. * @{
  234. */
  235. /**
  236. * @brief Enable AHB1 peripherals clock.
  237. * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
  238. * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
  239. * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
  240. * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
  241. * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
  242. * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
  243. * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
  244. * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n
  245. * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
  246. * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n
  247. * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
  248. * @param Periphs This parameter can be a combination of the following values:
  249. * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
  250. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
  251. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
  252. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  253. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  254. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  255. * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
  256. * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
  257. * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
  258. * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
  259. * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
  260. *
  261. * (*) value not defined in all devices.
  262. * @retval None
  263. */
  264. __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
  265. {
  266. __IO uint32_t tmpreg;
  267. SET_BIT(RCC->AHBENR, Periphs);
  268. /* Delay after an RCC peripheral clock enabling */
  269. tmpreg = READ_BIT(RCC->AHBENR, Periphs);
  270. (void)tmpreg;
  271. }
  272. /**
  273. * @brief Check if AHB1 peripheral clock is enabled or not
  274. * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
  275. * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
  276. * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
  277. * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
  278. * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
  279. * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
  280. * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
  281. * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n
  282. * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
  283. * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n
  284. * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
  285. * @param Periphs This parameter can be a combination of the following values:
  286. * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
  287. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
  288. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
  289. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  290. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  291. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  292. * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
  293. * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
  294. * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
  295. * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
  296. * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
  297. *
  298. * (*) value not defined in all devices.
  299. * @retval State of Periphs (1 or 0).
  300. */
  301. __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
  302. {
  303. return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
  304. }
  305. /**
  306. * @brief Disable AHB1 peripherals clock.
  307. * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
  308. * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
  309. * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
  310. * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
  311. * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
  312. * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
  313. * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
  314. * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n
  315. * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
  316. * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n
  317. * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
  318. * @param Periphs This parameter can be a combination of the following values:
  319. * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
  320. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
  321. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
  322. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  323. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  324. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  325. * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
  326. * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
  327. * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
  328. * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
  329. * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
  330. *
  331. * (*) value not defined in all devices.
  332. * @retval None
  333. */
  334. __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
  335. {
  336. CLEAR_BIT(RCC->AHBENR, Periphs);
  337. }
  338. #if defined(RCC_AHBRSTR_SUPPORT)
  339. /**
  340. * @brief Force AHB1 peripherals reset.
  341. * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
  342. * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset
  343. * @param Periphs This parameter can be a combination of the following values:
  344. * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
  345. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  346. * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
  347. *
  348. * (*) value not defined in all devices.
  349. * @retval None
  350. */
  351. __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
  352. {
  353. SET_BIT(RCC->AHBRSTR, Periphs);
  354. }
  355. /**
  356. * @brief Release AHB1 peripherals reset.
  357. * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
  358. * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset
  359. * @param Periphs This parameter can be a combination of the following values:
  360. * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
  361. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  362. * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
  363. *
  364. * (*) value not defined in all devices.
  365. * @retval None
  366. */
  367. __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
  368. {
  369. CLEAR_BIT(RCC->AHBRSTR, Periphs);
  370. }
  371. #endif /* RCC_AHBRSTR_SUPPORT */
  372. /**
  373. * @}
  374. */
  375. /** @defgroup BUS_LL_EF_APB1 APB1
  376. * @{
  377. */
  378. /**
  379. * @brief Enable APB1 peripherals clock.
  380. * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n
  381. * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
  382. * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
  383. * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
  384. * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
  385. * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
  386. * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
  387. * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
  388. * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
  389. * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
  390. * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
  391. * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
  392. * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
  393. * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
  394. * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
  395. * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
  396. * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
  397. * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
  398. * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
  399. * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
  400. * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
  401. * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
  402. * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
  403. * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
  404. * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
  405. * @param Periphs This parameter can be a combination of the following values:
  406. * @arg @ref LL_APB1_GRP1_PERIPH_BKP
  407. * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
  408. * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
  409. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  410. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  411. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  412. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  413. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  414. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  415. * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
  416. * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
  417. * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
  418. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
  419. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
  420. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  421. * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
  422. * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
  423. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  424. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  425. * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
  426. * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
  427. * @arg @ref LL_APB1_GRP1_PERIPH_USART2
  428. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  429. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  430. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  431. *
  432. * (*) value not defined in all devices.
  433. * @retval None
  434. */
  435. __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
  436. {
  437. __IO uint32_t tmpreg;
  438. SET_BIT(RCC->APB1ENR, Periphs);
  439. /* Delay after an RCC peripheral clock enabling */
  440. tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
  441. (void)tmpreg;
  442. }
  443. /**
  444. * @brief Check if APB1 peripheral clock is enabled or not
  445. * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n
  446. * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
  447. * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
  448. * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
  449. * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
  450. * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
  451. * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
  452. * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
  453. * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
  454. * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
  455. * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
  456. * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
  457. * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
  458. * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
  459. * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
  460. * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
  461. * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
  462. * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
  463. * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
  464. * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
  465. * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
  466. * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
  467. * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
  468. * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
  469. * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
  470. * @param Periphs This parameter can be a combination of the following values:
  471. * @arg @ref LL_APB1_GRP1_PERIPH_BKP
  472. * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
  473. * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
  474. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  475. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  476. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  477. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  478. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  479. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  480. * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
  481. * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
  482. * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
  483. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
  484. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
  485. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  486. * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
  487. * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
  488. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  489. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  490. * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
  491. * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
  492. * @arg @ref LL_APB1_GRP1_PERIPH_USART2
  493. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  494. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  495. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  496. *
  497. * (*) value not defined in all devices.
  498. * @retval State of Periphs (1 or 0).
  499. */
  500. __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
  501. {
  502. return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
  503. }
  504. /**
  505. * @brief Disable APB1 peripherals clock.
  506. * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n
  507. * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
  508. * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
  509. * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
  510. * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
  511. * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
  512. * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
  513. * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
  514. * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
  515. * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
  516. * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
  517. * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
  518. * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
  519. * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
  520. * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
  521. * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
  522. * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
  523. * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
  524. * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
  525. * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
  526. * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
  527. * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
  528. * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
  529. * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
  530. * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
  531. * @param Periphs This parameter can be a combination of the following values:
  532. * @arg @ref LL_APB1_GRP1_PERIPH_BKP
  533. * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
  534. * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
  535. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  536. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  537. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  538. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  539. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  540. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  541. * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
  542. * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
  543. * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
  544. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
  545. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
  546. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  547. * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
  548. * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
  549. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  550. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  551. * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
  552. * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
  553. * @arg @ref LL_APB1_GRP1_PERIPH_USART2
  554. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  555. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  556. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  557. *
  558. * (*) value not defined in all devices.
  559. * @retval None
  560. */
  561. __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
  562. {
  563. CLEAR_BIT(RCC->APB1ENR, Periphs);
  564. }
  565. /**
  566. * @brief Force APB1 peripherals reset.
  567. * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n
  568. * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
  569. * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
  570. * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
  571. * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
  572. * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
  573. * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
  574. * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
  575. * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
  576. * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
  577. * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
  578. * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
  579. * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
  580. * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
  581. * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
  582. * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
  583. * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
  584. * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
  585. * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
  586. * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
  587. * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
  588. * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
  589. * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
  590. * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
  591. * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
  592. * @param Periphs This parameter can be a combination of the following values:
  593. * @arg @ref LL_APB1_GRP1_PERIPH_ALL
  594. * @arg @ref LL_APB1_GRP1_PERIPH_BKP
  595. * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
  596. * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
  597. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  598. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  599. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  600. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  601. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  602. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  603. * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
  604. * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
  605. * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
  606. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
  607. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
  608. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  609. * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
  610. * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
  611. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  612. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  613. * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
  614. * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
  615. * @arg @ref LL_APB1_GRP1_PERIPH_USART2
  616. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  617. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  618. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  619. *
  620. * (*) value not defined in all devices.
  621. * @retval None
  622. */
  623. __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
  624. {
  625. SET_BIT(RCC->APB1RSTR, Periphs);
  626. }
  627. /**
  628. * @brief Release APB1 peripherals reset.
  629. * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n
  630. * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
  631. * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
  632. * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
  633. * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
  634. * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
  635. * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
  636. * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
  637. * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
  638. * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
  639. * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
  640. * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
  641. * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
  642. * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
  643. * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
  644. * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
  645. * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
  646. * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
  647. * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
  648. * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
  649. * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
  650. * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
  651. * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
  652. * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
  653. * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
  654. * @param Periphs This parameter can be a combination of the following values:
  655. * @arg @ref LL_APB1_GRP1_PERIPH_ALL
  656. * @arg @ref LL_APB1_GRP1_PERIPH_BKP
  657. * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
  658. * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
  659. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  660. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  661. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  662. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  663. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  664. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  665. * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
  666. * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
  667. * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
  668. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
  669. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
  670. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  671. * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
  672. * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
  673. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  674. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  675. * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
  676. * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
  677. * @arg @ref LL_APB1_GRP1_PERIPH_USART2
  678. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  679. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  680. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  681. *
  682. * (*) value not defined in all devices.
  683. * @retval None
  684. */
  685. __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
  686. {
  687. CLEAR_BIT(RCC->APB1RSTR, Periphs);
  688. }
  689. /**
  690. * @}
  691. */
  692. /** @defgroup BUS_LL_EF_APB2 APB2
  693. * @{
  694. */
  695. /**
  696. * @brief Enable APB2 peripherals clock.
  697. * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
  698. * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
  699. * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
  700. * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n
  701. * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n
  702. * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n
  703. * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n
  704. * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n
  705. * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n
  706. * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n
  707. * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n
  708. * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
  709. * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
  710. * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
  711. * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
  712. * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
  713. * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
  714. * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
  715. * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
  716. * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
  717. * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
  718. * @param Periphs This parameter can be a combination of the following values:
  719. * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
  720. * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
  721. * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
  722. * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
  723. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
  724. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
  725. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
  726. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
  727. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
  728. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
  729. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
  730. * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
  731. * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
  732. * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
  733. * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
  734. * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
  735. * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
  736. * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
  737. * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
  738. * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
  739. * @arg @ref LL_APB2_GRP1_PERIPH_USART1
  740. *
  741. * (*) value not defined in all devices.
  742. * @retval None
  743. */
  744. __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
  745. {
  746. __IO uint32_t tmpreg;
  747. SET_BIT(RCC->APB2ENR, Periphs);
  748. /* Delay after an RCC peripheral clock enabling */
  749. tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
  750. (void)tmpreg;
  751. }
  752. /**
  753. * @brief Check if APB2 peripheral clock is enabled or not
  754. * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
  755. * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
  756. * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
  757. * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n
  758. * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n
  759. * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n
  760. * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n
  761. * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n
  762. * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n
  763. * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n
  764. * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n
  765. * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
  766. * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
  767. * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
  768. * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
  769. * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
  770. * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
  771. * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
  772. * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
  773. * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
  774. * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
  775. * @param Periphs This parameter can be a combination of the following values:
  776. * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
  777. * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
  778. * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
  779. * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
  780. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
  781. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
  782. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
  783. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
  784. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
  785. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
  786. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
  787. * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
  788. * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
  789. * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
  790. * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
  791. * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
  792. * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
  793. * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
  794. * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
  795. * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
  796. * @arg @ref LL_APB2_GRP1_PERIPH_USART1
  797. *
  798. * (*) value not defined in all devices.
  799. * @retval State of Periphs (1 or 0).
  800. */
  801. __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
  802. {
  803. return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
  804. }
  805. /**
  806. * @brief Disable APB2 peripherals clock.
  807. * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
  808. * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
  809. * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
  810. * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n
  811. * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n
  812. * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n
  813. * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n
  814. * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n
  815. * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n
  816. * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n
  817. * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n
  818. * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
  819. * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
  820. * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
  821. * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
  822. * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
  823. * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
  824. * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
  825. * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
  826. * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
  827. * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
  828. * @param Periphs This parameter can be a combination of the following values:
  829. * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
  830. * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
  831. * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
  832. * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
  833. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
  834. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
  835. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
  836. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
  837. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
  838. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
  839. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
  840. * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
  841. * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
  842. * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
  843. * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
  844. * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
  845. * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
  846. * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
  847. * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
  848. * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
  849. * @arg @ref LL_APB2_GRP1_PERIPH_USART1
  850. *
  851. * (*) value not defined in all devices.
  852. * @retval None
  853. */
  854. __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
  855. {
  856. CLEAR_BIT(RCC->APB2ENR, Periphs);
  857. }
  858. /**
  859. * @brief Force APB2 peripherals reset.
  860. * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
  861. * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n
  862. * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n
  863. * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n
  864. * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n
  865. * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n
  866. * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n
  867. * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n
  868. * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n
  869. * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n
  870. * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n
  871. * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
  872. * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
  873. * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
  874. * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
  875. * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
  876. * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
  877. * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
  878. * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
  879. * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
  880. * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
  881. * @param Periphs This parameter can be a combination of the following values:
  882. * @arg @ref LL_APB2_GRP1_PERIPH_ALL
  883. * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
  884. * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
  885. * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
  886. * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
  887. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
  888. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
  889. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
  890. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
  891. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
  892. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
  893. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
  894. * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
  895. * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
  896. * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
  897. * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
  898. * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
  899. * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
  900. * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
  901. * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
  902. * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
  903. * @arg @ref LL_APB2_GRP1_PERIPH_USART1
  904. *
  905. * (*) value not defined in all devices.
  906. * @retval None
  907. */
  908. __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
  909. {
  910. SET_BIT(RCC->APB2RSTR, Periphs);
  911. }
  912. /**
  913. * @brief Release APB2 peripherals reset.
  914. * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
  915. * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n
  916. * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n
  917. * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n
  918. * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n
  919. * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n
  920. * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n
  921. * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n
  922. * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n
  923. * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n
  924. * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n
  925. * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
  926. * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
  927. * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
  928. * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
  929. * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
  930. * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
  931. * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
  932. * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
  933. * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
  934. * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
  935. * @param Periphs This parameter can be a combination of the following values:
  936. * @arg @ref LL_APB2_GRP1_PERIPH_ALL
  937. * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
  938. * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
  939. * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
  940. * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
  941. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
  942. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
  943. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
  944. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
  945. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
  946. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
  947. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
  948. * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
  949. * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
  950. * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
  951. * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
  952. * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
  953. * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
  954. * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
  955. * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
  956. * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
  957. * @arg @ref LL_APB2_GRP1_PERIPH_USART1
  958. *
  959. * (*) value not defined in all devices.
  960. * @retval None
  961. */
  962. __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
  963. {
  964. CLEAR_BIT(RCC->APB2RSTR, Periphs);
  965. }
  966. /**
  967. * @}
  968. */
  969. /**
  970. * @}
  971. */
  972. /**
  973. * @}
  974. */
  975. #endif /* defined(RCC) */
  976. /**
  977. * @}
  978. */
  979. #ifdef __cplusplus
  980. }
  981. #endif
  982. #endif /* __STM32F1xx_LL_BUS_H */
  983. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/