startup_stm32f101xg.s 15 KB

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  1. ;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
  2. ;* File Name : startup_stm32f101xg.s
  3. ;* Author : MCD Application Team
  4. ;* Version : V4.2.0
  5. ;* Date : 31-March-2017
  6. ;* Description : STM32F101xG Devices vector table for MDK-ARM toolchain.
  7. ;* This module performs:
  8. ;* - Set the initial SP
  9. ;* - Set the initial PC == Reset_Handler
  10. ;* - Set the vector table entries with the exceptions ISR address
  11. ;* - Configure the clock system
  12. ;* - Branches to __main in the C library (which eventually
  13. ;* calls main()).
  14. ;* After Reset the Cortex-M3 processor is in Thread mode,
  15. ;* priority is Privileged, and the Stack is set to Main.
  16. ;********************************************************************************
  17. ;*
  18. ;* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  19. ;*
  20. ;* Redistribution and use in source and binary forms, with or without modification,
  21. ;* are permitted provided that the following conditions are met:
  22. ;* 1. Redistributions of source code must retain the above copyright notice,
  23. ;* this list of conditions and the following disclaimer.
  24. ;* 2. Redistributions in binary form must reproduce the above copyright notice,
  25. ;* this list of conditions and the following disclaimer in the documentation
  26. ;* and/or other materials provided with the distribution.
  27. ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
  28. ;* may be used to endorse or promote products derived from this software
  29. ;* without specific prior written permission.
  30. ;*
  31. ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  32. ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  33. ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  34. ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  35. ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  36. ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  37. ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  38. ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  39. ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  40. ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41. ;
  42. ;*******************************************************************************
  43. ; Amount of memory (in bytes) allocated for Stack
  44. ; Tailor this value to your application needs
  45. ; <h> Stack Configuration
  46. ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  47. ; </h>
  48. Stack_Size EQU 0x00000400
  49. AREA STACK, NOINIT, READWRITE, ALIGN=3
  50. Stack_Mem SPACE Stack_Size
  51. __initial_sp
  52. ; <h> Heap Configuration
  53. ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  54. ; </h>
  55. Heap_Size EQU 0x00000200
  56. AREA HEAP, NOINIT, READWRITE, ALIGN=3
  57. __heap_base
  58. Heap_Mem SPACE Heap_Size
  59. __heap_limit
  60. PRESERVE8
  61. THUMB
  62. ; Vector Table Mapped to Address 0 at Reset
  63. AREA RESET, DATA, READONLY
  64. EXPORT __Vectors
  65. EXPORT __Vectors_End
  66. EXPORT __Vectors_Size
  67. __Vectors DCD __initial_sp ; Top of Stack
  68. DCD Reset_Handler ; Reset Handler
  69. DCD NMI_Handler ; NMI Handler
  70. DCD HardFault_Handler ; Hard Fault Handler
  71. DCD MemManage_Handler ; MPU Fault Handler
  72. DCD BusFault_Handler ; Bus Fault Handler
  73. DCD UsageFault_Handler ; Usage Fault Handler
  74. DCD 0 ; Reserved
  75. DCD 0 ; Reserved
  76. DCD 0 ; Reserved
  77. DCD 0 ; Reserved
  78. DCD SVC_Handler ; SVCall Handler
  79. DCD DebugMon_Handler ; Debug Monitor Handler
  80. DCD 0 ; Reserved
  81. DCD PendSV_Handler ; PendSV Handler
  82. DCD SysTick_Handler ; SysTick Handler
  83. ; External Interrupts
  84. DCD WWDG_IRQHandler ; Window Watchdog
  85. DCD PVD_IRQHandler ; PVD through EXTI Line detect
  86. DCD TAMPER_IRQHandler ; Tamper
  87. DCD RTC_IRQHandler ; RTC
  88. DCD FLASH_IRQHandler ; Flash
  89. DCD RCC_IRQHandler ; RCC
  90. DCD EXTI0_IRQHandler ; EXTI Line 0
  91. DCD EXTI1_IRQHandler ; EXTI Line 1
  92. DCD EXTI2_IRQHandler ; EXTI Line 2
  93. DCD EXTI3_IRQHandler ; EXTI Line 3
  94. DCD EXTI4_IRQHandler ; EXTI Line 4
  95. DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
  96. DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
  97. DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
  98. DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
  99. DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
  100. DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
  101. DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
  102. DCD ADC1_2_IRQHandler ; ADC1_2
  103. DCD 0 ; Reserved
  104. DCD 0 ; Reserved
  105. DCD 0 ; Reserved
  106. DCD 0 ; Reserved
  107. DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
  108. DCD TIM9_IRQHandler ; TIM9
  109. DCD TIM10_IRQHandler ; TIM10
  110. DCD TIM11_IRQHandler ; TIM11
  111. DCD 0 ; Reserved
  112. DCD TIM2_IRQHandler ; TIM2
  113. DCD TIM3_IRQHandler ; TIM3
  114. DCD TIM4_IRQHandler ; TIM4
  115. DCD I2C1_EV_IRQHandler ; I2C1 Event
  116. DCD I2C1_ER_IRQHandler ; I2C1 Error
  117. DCD I2C2_EV_IRQHandler ; I2C2 Event
  118. DCD I2C2_ER_IRQHandler ; I2C2 Error
  119. DCD SPI1_IRQHandler ; SPI1
  120. DCD SPI2_IRQHandler ; SPI2
  121. DCD USART1_IRQHandler ; USART1
  122. DCD USART2_IRQHandler ; USART2
  123. DCD USART3_IRQHandler ; USART3
  124. DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
  125. DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
  126. DCD 0 ; Reserved
  127. DCD TIM12_IRQHandler ; TIM12
  128. DCD TIM13_IRQHandler ; TIM13
  129. DCD TIM14_IRQHandler ; TIM14
  130. DCD 0 ; Reserved
  131. DCD 0 ; Reserved
  132. DCD FSMC_IRQHandler ; FSMC
  133. DCD 0 ; Reserved
  134. DCD TIM5_IRQHandler ; TIM5
  135. DCD SPI3_IRQHandler ; SPI3
  136. DCD UART4_IRQHandler ; UART4
  137. DCD UART5_IRQHandler ; UART5
  138. DCD TIM6_IRQHandler ; TIM6
  139. DCD TIM7_IRQHandler ; TIM7
  140. DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
  141. DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
  142. DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
  143. DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
  144. __Vectors_End
  145. __Vectors_Size EQU __Vectors_End - __Vectors
  146. AREA |.text|, CODE, READONLY
  147. ; Reset handler
  148. Reset_Handler PROC
  149. EXPORT Reset_Handler [WEAK]
  150. IMPORT __main
  151. IMPORT SystemInit
  152. LDR R0, =SystemInit
  153. BLX R0
  154. LDR R0, =__main
  155. BX R0
  156. ENDP
  157. ; Dummy Exception Handlers (infinite loops which can be modified)
  158. NMI_Handler PROC
  159. EXPORT NMI_Handler [WEAK]
  160. B .
  161. ENDP
  162. HardFault_Handler\
  163. PROC
  164. EXPORT HardFault_Handler [WEAK]
  165. B .
  166. ENDP
  167. MemManage_Handler\
  168. PROC
  169. EXPORT MemManage_Handler [WEAK]
  170. B .
  171. ENDP
  172. BusFault_Handler\
  173. PROC
  174. EXPORT BusFault_Handler [WEAK]
  175. B .
  176. ENDP
  177. UsageFault_Handler\
  178. PROC
  179. EXPORT UsageFault_Handler [WEAK]
  180. B .
  181. ENDP
  182. SVC_Handler PROC
  183. EXPORT SVC_Handler [WEAK]
  184. B .
  185. ENDP
  186. DebugMon_Handler\
  187. PROC
  188. EXPORT DebugMon_Handler [WEAK]
  189. B .
  190. ENDP
  191. PendSV_Handler PROC
  192. EXPORT PendSV_Handler [WEAK]
  193. B .
  194. ENDP
  195. SysTick_Handler PROC
  196. EXPORT SysTick_Handler [WEAK]
  197. B .
  198. ENDP
  199. Default_Handler PROC
  200. EXPORT WWDG_IRQHandler [WEAK]
  201. EXPORT PVD_IRQHandler [WEAK]
  202. EXPORT TAMPER_IRQHandler [WEAK]
  203. EXPORT RTC_IRQHandler [WEAK]
  204. EXPORT FLASH_IRQHandler [WEAK]
  205. EXPORT RCC_IRQHandler [WEAK]
  206. EXPORT EXTI0_IRQHandler [WEAK]
  207. EXPORT EXTI1_IRQHandler [WEAK]
  208. EXPORT EXTI2_IRQHandler [WEAK]
  209. EXPORT EXTI3_IRQHandler [WEAK]
  210. EXPORT EXTI4_IRQHandler [WEAK]
  211. EXPORT DMA1_Channel1_IRQHandler [WEAK]
  212. EXPORT DMA1_Channel2_IRQHandler [WEAK]
  213. EXPORT DMA1_Channel3_IRQHandler [WEAK]
  214. EXPORT DMA1_Channel4_IRQHandler [WEAK]
  215. EXPORT DMA1_Channel5_IRQHandler [WEAK]
  216. EXPORT DMA1_Channel6_IRQHandler [WEAK]
  217. EXPORT DMA1_Channel7_IRQHandler [WEAK]
  218. EXPORT ADC1_2_IRQHandler [WEAK]
  219. EXPORT EXTI9_5_IRQHandler [WEAK]
  220. EXPORT TIM9_IRQHandler [WEAK]
  221. EXPORT TIM10_IRQHandler [WEAK]
  222. EXPORT TIM11_IRQHandler [WEAK]
  223. EXPORT TIM2_IRQHandler [WEAK]
  224. EXPORT TIM3_IRQHandler [WEAK]
  225. EXPORT TIM4_IRQHandler [WEAK]
  226. EXPORT I2C1_EV_IRQHandler [WEAK]
  227. EXPORT I2C1_ER_IRQHandler [WEAK]
  228. EXPORT I2C2_EV_IRQHandler [WEAK]
  229. EXPORT I2C2_ER_IRQHandler [WEAK]
  230. EXPORT SPI1_IRQHandler [WEAK]
  231. EXPORT SPI2_IRQHandler [WEAK]
  232. EXPORT USART1_IRQHandler [WEAK]
  233. EXPORT USART2_IRQHandler [WEAK]
  234. EXPORT USART3_IRQHandler [WEAK]
  235. EXPORT EXTI15_10_IRQHandler [WEAK]
  236. EXPORT RTC_Alarm_IRQHandler [WEAK]
  237. EXPORT TIM12_IRQHandler [WEAK]
  238. EXPORT TIM13_IRQHandler [WEAK]
  239. EXPORT TIM14_IRQHandler [WEAK]
  240. EXPORT FSMC_IRQHandler [WEAK]
  241. EXPORT TIM5_IRQHandler [WEAK]
  242. EXPORT SPI3_IRQHandler [WEAK]
  243. EXPORT UART4_IRQHandler [WEAK]
  244. EXPORT UART5_IRQHandler [WEAK]
  245. EXPORT TIM6_IRQHandler [WEAK]
  246. EXPORT TIM7_IRQHandler [WEAK]
  247. EXPORT DMA2_Channel1_IRQHandler [WEAK]
  248. EXPORT DMA2_Channel2_IRQHandler [WEAK]
  249. EXPORT DMA2_Channel3_IRQHandler [WEAK]
  250. EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
  251. WWDG_IRQHandler
  252. PVD_IRQHandler
  253. TAMPER_IRQHandler
  254. RTC_IRQHandler
  255. FLASH_IRQHandler
  256. RCC_IRQHandler
  257. EXTI0_IRQHandler
  258. EXTI1_IRQHandler
  259. EXTI2_IRQHandler
  260. EXTI3_IRQHandler
  261. EXTI4_IRQHandler
  262. DMA1_Channel1_IRQHandler
  263. DMA1_Channel2_IRQHandler
  264. DMA1_Channel3_IRQHandler
  265. DMA1_Channel4_IRQHandler
  266. DMA1_Channel5_IRQHandler
  267. DMA1_Channel6_IRQHandler
  268. DMA1_Channel7_IRQHandler
  269. ADC1_2_IRQHandler
  270. EXTI9_5_IRQHandler
  271. TIM9_IRQHandler
  272. TIM10_IRQHandler
  273. TIM11_IRQHandler
  274. TIM2_IRQHandler
  275. TIM3_IRQHandler
  276. TIM4_IRQHandler
  277. I2C1_EV_IRQHandler
  278. I2C1_ER_IRQHandler
  279. I2C2_EV_IRQHandler
  280. I2C2_ER_IRQHandler
  281. SPI1_IRQHandler
  282. SPI2_IRQHandler
  283. USART1_IRQHandler
  284. USART2_IRQHandler
  285. USART3_IRQHandler
  286. EXTI15_10_IRQHandler
  287. RTC_Alarm_IRQHandler
  288. TIM12_IRQHandler
  289. TIM13_IRQHandler
  290. TIM14_IRQHandler
  291. FSMC_IRQHandler
  292. TIM5_IRQHandler
  293. SPI3_IRQHandler
  294. UART4_IRQHandler
  295. UART5_IRQHandler
  296. TIM6_IRQHandler
  297. TIM7_IRQHandler
  298. DMA2_Channel1_IRQHandler
  299. DMA2_Channel2_IRQHandler
  300. DMA2_Channel3_IRQHandler
  301. DMA2_Channel4_5_IRQHandler
  302. B .
  303. ENDP
  304. ALIGN
  305. ;*******************************************************************************
  306. ; User Stack and Heap initialization
  307. ;*******************************************************************************
  308. IF :DEF:__MICROLIB
  309. EXPORT __initial_sp
  310. EXPORT __heap_base
  311. EXPORT __heap_limit
  312. ELSE
  313. IMPORT __use_two_region_memory
  314. EXPORT __user_initial_stackheap
  315. __user_initial_stackheap
  316. LDR R0, = Heap_Mem
  317. LDR R1, =(Stack_Mem + Stack_Size)
  318. LDR R2, = (Heap_Mem + Heap_Size)
  319. LDR R3, = Stack_Mem
  320. BX LR
  321. ALIGN
  322. ENDIF
  323. END
  324. ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****