stm32f1xx_ll_utils.c 24 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_ll_utils.c
  4. * @author MCD Application Team
  5. * @brief UTILS LL module driver.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10. *
  11. * Redistribution and use in source and binary forms, with or without modification,
  12. * are permitted provided that the following conditions are met:
  13. * 1. Redistributions of source code must retain the above copyright notice,
  14. * this list of conditions and the following disclaimer.
  15. * 2. Redistributions in binary form must reproduce the above copyright notice,
  16. * this list of conditions and the following disclaimer in the documentation
  17. * and/or other materials provided with the distribution.
  18. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  19. * may be used to endorse or promote products derived from this software
  20. * without specific prior written permission.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. ******************************************************************************
  34. */
  35. /* Includes ------------------------------------------------------------------*/
  36. #include "stm32f1xx_ll_rcc.h"
  37. #include "stm32f1xx_ll_utils.h"
  38. #include "stm32f1xx_ll_system.h"
  39. #ifdef USE_FULL_ASSERT
  40. #include "stm32_assert.h"
  41. #else
  42. #define assert_param(expr) ((void)0U)
  43. #endif
  44. /** @addtogroup STM32F1xx_LL_Driver
  45. * @{
  46. */
  47. /** @addtogroup UTILS_LL
  48. * @{
  49. */
  50. /* Private types -------------------------------------------------------------*/
  51. /* Private variables ---------------------------------------------------------*/
  52. /* Private constants ---------------------------------------------------------*/
  53. /** @addtogroup UTILS_LL_Private_Constants
  54. * @{
  55. */
  56. /* Defines used for PLL range */
  57. #define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */
  58. /* Defines used for HSE range */
  59. #define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */
  60. #define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */
  61. /* Defines used for FLASH latency according to HCLK Frequency */
  62. #if defined(FLASH_ACR_LATENCY)
  63. #define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
  64. #define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
  65. #else
  66. /*!< No Latency Configuration in this device */
  67. #endif
  68. /**
  69. * @}
  70. */
  71. /* Private macros ------------------------------------------------------------*/
  72. /** @addtogroup UTILS_LL_Private_Macros
  73. * @{
  74. */
  75. #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
  76. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
  77. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
  78. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
  79. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
  80. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
  81. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
  82. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
  83. || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
  84. #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
  85. || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
  86. || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
  87. || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
  88. || ((__VALUE__) == LL_RCC_APB1_DIV_16))
  89. #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
  90. || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
  91. || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
  92. || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
  93. || ((__VALUE__) == LL_RCC_APB2_DIV_16))
  94. #if defined(RCC_CFGR_PLLMULL6_5)
  95. #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
  96. || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
  97. || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
  98. || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
  99. || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
  100. || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
  101. || ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
  102. #else
  103. #define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
  104. || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
  105. || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
  106. || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
  107. || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
  108. || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
  109. || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
  110. || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
  111. || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
  112. || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
  113. || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
  114. || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
  115. || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
  116. || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
  117. || ((__VALUE__) == LL_RCC_PLL_MUL_16))
  118. #endif /* RCC_CFGR_PLLMULL6_5 */
  119. #if defined(RCC_CFGR2_PREDIV1)
  120. #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
  121. ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
  122. ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
  123. ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
  124. ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
  125. ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
  126. ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
  127. ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
  128. #else
  129. #define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
  130. #endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
  131. #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
  132. #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
  133. || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
  134. #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
  135. /**
  136. * @}
  137. */
  138. /* Private function prototypes -----------------------------------------------*/
  139. /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
  140. * @{
  141. */
  142. static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
  143. LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
  144. #if defined(FLASH_ACR_LATENCY)
  145. static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
  146. #endif /* FLASH_ACR_LATENCY */
  147. static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
  148. static ErrorStatus UTILS_PLL_IsBusy(void);
  149. /**
  150. * @}
  151. */
  152. /* Exported functions --------------------------------------------------------*/
  153. /** @addtogroup UTILS_LL_Exported_Functions
  154. * @{
  155. */
  156. /** @addtogroup UTILS_LL_EF_DELAY
  157. * @{
  158. */
  159. /**
  160. * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
  161. * @note When a RTOS is used, it is recommended to avoid changing the Systick
  162. * configuration by calling this function, for a delay use rather osDelay RTOS service.
  163. * @param HCLKFrequency HCLK frequency in Hz
  164. * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
  165. * @retval None
  166. */
  167. void LL_Init1msTick(uint32_t HCLKFrequency)
  168. {
  169. /* Use frequency provided in argument */
  170. LL_InitTick(HCLKFrequency, 1000U);
  171. }
  172. /**
  173. * @brief This function provides accurate delay (in milliseconds) based
  174. * on SysTick counter flag
  175. * @note When a RTOS is used, it is recommended to avoid using blocking delay
  176. * and use rather osDelay service.
  177. * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
  178. * will configure Systick to 1ms
  179. * @param Delay specifies the delay time length, in milliseconds.
  180. * @retval None
  181. */
  182. void LL_mDelay(uint32_t Delay)
  183. {
  184. __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
  185. /* Add this code to indicate that local variable is not used */
  186. ((void)tmp);
  187. /* Add a period to guaranty minimum wait */
  188. if (Delay < LL_MAX_DELAY)
  189. {
  190. Delay++;
  191. }
  192. while (Delay)
  193. {
  194. if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
  195. {
  196. Delay--;
  197. }
  198. }
  199. }
  200. /**
  201. * @}
  202. */
  203. /** @addtogroup UTILS_EF_SYSTEM
  204. * @brief System Configuration functions
  205. *
  206. @verbatim
  207. ===============================================================================
  208. ##### System Configuration functions #####
  209. ===============================================================================
  210. [..]
  211. System, AHB and APB buses clocks configuration
  212. (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
  213. @endverbatim
  214. @internal
  215. Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
  216. (++) +-----------------------------------------------+
  217. (++) | Latency | SYSCLK clock frequency (MHz) |
  218. (++) |---------------|-------------------------------|
  219. (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
  220. (++) |---------------|-------------------------------|
  221. (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
  222. (++) |---------------|-------------------------------|
  223. (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
  224. (++) +-----------------------------------------------+
  225. @endinternal
  226. * @{
  227. */
  228. /**
  229. * @brief This function sets directly SystemCoreClock CMSIS variable.
  230. * @note Variable can be calculated also through SystemCoreClockUpdate function.
  231. * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
  232. * @retval None
  233. */
  234. void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
  235. {
  236. /* HCLK clock frequency */
  237. SystemCoreClock = HCLKFrequency;
  238. }
  239. /**
  240. * @brief This function configures system clock with HSI as clock source of the PLL
  241. * @note The application need to ensure that PLL is disabled.
  242. * @note Function is based on the following formula:
  243. * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
  244. * - PREDIV: Set to 2 for few devices
  245. * - PLLMUL: The application software must set correctly the PLL multiplication factor to
  246. * not exceed 72MHz
  247. * @note FLASH latency can be modified through this function.
  248. * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
  249. * the configuration information for the PLL.
  250. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  251. * the configuration information for the BUS prescalers.
  252. * @retval An ErrorStatus enumeration value:
  253. * - SUCCESS: Max frequency configuration done
  254. * - ERROR: Max frequency configuration not done
  255. */
  256. ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
  257. LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
  258. {
  259. ErrorStatus status = SUCCESS;
  260. uint32_t pllfreq = 0U;
  261. /* Check if one of the PLL is enabled */
  262. if (UTILS_PLL_IsBusy() == SUCCESS)
  263. {
  264. #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
  265. /* Check PREDIV value */
  266. assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
  267. #else
  268. /* Force PREDIV value to 2 */
  269. UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
  270. #endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
  271. /* Calculate the new PLL output frequency */
  272. pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
  273. /* Enable HSI if not enabled */
  274. if (LL_RCC_HSI_IsReady() != 1U)
  275. {
  276. LL_RCC_HSI_Enable();
  277. while (LL_RCC_HSI_IsReady() != 1U)
  278. {
  279. /* Wait for HSI ready */
  280. }
  281. }
  282. /* Configure PLL */
  283. LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
  284. /* Enable PLL and switch system clock to PLL */
  285. status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
  286. }
  287. else
  288. {
  289. /* Current PLL configuration cannot be modified */
  290. status = ERROR;
  291. }
  292. return status;
  293. }
  294. /**
  295. * @brief This function configures system clock with HSE as clock source of the PLL
  296. * @note The application need to ensure that PLL is disabled.
  297. * @note Function is based on the following formula:
  298. * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
  299. * - PREDIV: Set to 2 for few devices
  300. * - PLLMUL: The application software must set correctly the PLL multiplication factor to
  301. * not exceed @ref UTILS_PLL_OUTPUT_MAX
  302. * @note FLASH latency can be modified through this function.
  303. * @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
  304. * @param HSEBypass This parameter can be one of the following values:
  305. * @arg @ref LL_UTILS_HSEBYPASS_ON
  306. * @arg @ref LL_UTILS_HSEBYPASS_OFF
  307. * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
  308. * the configuration information for the PLL.
  309. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  310. * the configuration information for the BUS prescalers.
  311. * @retval An ErrorStatus enumeration value:
  312. * - SUCCESS: Max frequency configuration done
  313. * - ERROR: Max frequency configuration not done
  314. */
  315. ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
  316. LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
  317. {
  318. ErrorStatus status = SUCCESS;
  319. uint32_t pllfreq = 0U;
  320. /* Check the parameters */
  321. assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
  322. assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
  323. /* Check if one of the PLL is enabled */
  324. if (UTILS_PLL_IsBusy() == SUCCESS)
  325. {
  326. assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
  327. /* Calculate the new PLL output frequency */
  328. pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
  329. /* Enable HSE if not enabled */
  330. if (LL_RCC_HSE_IsReady() != 1U)
  331. {
  332. /* Check if need to enable HSE bypass feature or not */
  333. if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
  334. {
  335. LL_RCC_HSE_EnableBypass();
  336. }
  337. else
  338. {
  339. LL_RCC_HSE_DisableBypass();
  340. }
  341. /* Enable HSE */
  342. LL_RCC_HSE_Enable();
  343. while (LL_RCC_HSE_IsReady() != 1U)
  344. {
  345. /* Wait for HSE ready */
  346. }
  347. }
  348. /* Configure PLL */
  349. LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
  350. /* Enable PLL and switch system clock to PLL */
  351. status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
  352. }
  353. else
  354. {
  355. /* Current PLL configuration cannot be modified */
  356. status = ERROR;
  357. }
  358. return status;
  359. }
  360. /**
  361. * @}
  362. */
  363. /**
  364. * @}
  365. */
  366. /** @addtogroup UTILS_LL_Private_Functions
  367. * @{
  368. */
  369. /**
  370. * @brief Update number of Flash wait states in line with new frequency and current
  371. voltage range.
  372. * @param Frequency SYSCLK frequency
  373. * @retval An ErrorStatus enumeration value:
  374. * - SUCCESS: Latency has been modified
  375. * - ERROR: Latency cannot be modified
  376. */
  377. #if defined(FLASH_ACR_LATENCY)
  378. static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
  379. {
  380. ErrorStatus status = SUCCESS;
  381. uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
  382. /* Frequency cannot be equal to 0 */
  383. if (Frequency == 0U)
  384. {
  385. status = ERROR;
  386. }
  387. else
  388. {
  389. if (Frequency > UTILS_LATENCY2_FREQ)
  390. {
  391. /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
  392. latency = LL_FLASH_LATENCY_2;
  393. }
  394. else
  395. {
  396. if (Frequency > UTILS_LATENCY1_FREQ)
  397. {
  398. /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
  399. latency = LL_FLASH_LATENCY_1;
  400. }
  401. /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
  402. }
  403. LL_FLASH_SetLatency(latency);
  404. /* Check that the new number of wait states is taken into account to access the Flash
  405. memory by reading the FLASH_ACR register */
  406. if (LL_FLASH_GetLatency() != latency)
  407. {
  408. status = ERROR;
  409. }
  410. }
  411. return status;
  412. }
  413. #endif /* FLASH_ACR_LATENCY */
  414. /**
  415. * @brief Function to check that PLL can be modified
  416. * @param PLL_InputFrequency PLL input frequency (in Hz)
  417. * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
  418. * the configuration information for the PLL.
  419. * @retval PLL output frequency (in Hz)
  420. */
  421. static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
  422. {
  423. uint32_t pllfreq = 0U;
  424. /* Check the parameters */
  425. assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
  426. /* Check different PLL parameters according to RM */
  427. #if defined (RCC_CFGR2_PREDIV1)
  428. pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
  429. #elif defined(RCC_CFGR2_PREDIV1SRC)
  430. pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
  431. #else
  432. pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
  433. #endif /*RCC_CFGR2_PREDIV1SRC*/
  434. assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
  435. return pllfreq;
  436. }
  437. /**
  438. * @brief Function to check that PLL can be modified
  439. * @retval An ErrorStatus enumeration value:
  440. * - SUCCESS: PLL modification can be done
  441. * - ERROR: PLL is busy
  442. */
  443. static ErrorStatus UTILS_PLL_IsBusy(void)
  444. {
  445. ErrorStatus status = SUCCESS;
  446. /* Check if PLL is busy*/
  447. if (LL_RCC_PLL_IsReady() != 0U)
  448. {
  449. /* PLL configuration cannot be modified */
  450. status = ERROR;
  451. }
  452. #if defined(RCC_PLL2_SUPPORT)
  453. /* Check if PLL2 is busy*/
  454. if (LL_RCC_PLL2_IsReady() != 0U)
  455. {
  456. /* PLL2 configuration cannot be modified */
  457. status = ERROR;
  458. }
  459. #endif /* RCC_PLL2_SUPPORT */
  460. #if defined(RCC_PLLI2S_SUPPORT)
  461. /* Check if PLLI2S is busy*/
  462. if (LL_RCC_PLLI2S_IsReady() != 0U)
  463. {
  464. /* PLLI2S configuration cannot be modified */
  465. status = ERROR;
  466. }
  467. #endif /* RCC_PLLI2S_SUPPORT */
  468. return status;
  469. }
  470. /**
  471. * @brief Function to enable PLL and switch system clock to PLL
  472. * @param SYSCLK_Frequency SYSCLK frequency
  473. * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  474. * the configuration information for the BUS prescalers.
  475. * @retval An ErrorStatus enumeration value:
  476. * - SUCCESS: No problem to switch system to PLL
  477. * - ERROR: Problem to switch system to PLL
  478. */
  479. static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
  480. {
  481. ErrorStatus status = SUCCESS;
  482. #if defined(FLASH_ACR_LATENCY)
  483. uint32_t sysclk_frequency_current = 0U;
  484. #endif /* FLASH_ACR_LATENCY */
  485. assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
  486. assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
  487. assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
  488. #if defined(FLASH_ACR_LATENCY)
  489. /* Calculate current SYSCLK frequency */
  490. sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
  491. #endif /* FLASH_ACR_LATENCY */
  492. /* Increasing the number of wait states because of higher CPU frequency */
  493. #if defined (FLASH_ACR_LATENCY)
  494. if (sysclk_frequency_current < SYSCLK_Frequency)
  495. {
  496. /* Set FLASH latency to highest latency */
  497. status = UTILS_SetFlashLatency(SYSCLK_Frequency);
  498. }
  499. #endif /* FLASH_ACR_LATENCY */
  500. /* Update system clock configuration */
  501. if (status == SUCCESS)
  502. {
  503. #if defined(RCC_PLL2_SUPPORT)
  504. /* Enable PLL2 */
  505. LL_RCC_PLL2_Enable();
  506. while (LL_RCC_PLL2_IsReady() != 1U)
  507. {
  508. /* Wait for PLL2 ready */
  509. }
  510. #endif /* RCC_PLL2_SUPPORT */
  511. /* Enable PLL */
  512. LL_RCC_PLL_Enable();
  513. while (LL_RCC_PLL_IsReady() != 1U)
  514. {
  515. /* Wait for PLL ready */
  516. }
  517. /* Sysclk activation on the main PLL */
  518. LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
  519. LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
  520. while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
  521. {
  522. /* Wait for system clock switch to PLL */
  523. }
  524. /* Set APB1 & APB2 prescaler*/
  525. LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
  526. LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
  527. }
  528. /* Decreasing the number of wait states because of lower CPU frequency */
  529. #if defined (FLASH_ACR_LATENCY)
  530. if (sysclk_frequency_current > SYSCLK_Frequency)
  531. {
  532. /* Set FLASH latency to lowest latency */
  533. status = UTILS_SetFlashLatency(SYSCLK_Frequency);
  534. }
  535. #endif /* FLASH_ACR_LATENCY */
  536. /* Update SystemCoreClock variable */
  537. if (status == SUCCESS)
  538. {
  539. LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
  540. }
  541. return status;
  542. }
  543. /**
  544. * @}
  545. */
  546. /**
  547. * @}
  548. */
  549. /**
  550. * @}
  551. */
  552. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/